1. Field of the Invention
The present invention relates to an electronic exchange apparatus for a digital network such as an Integrated Service Digital Network (ISDN).
2. Description of the Related Art
With the advance of communication technology and diversification of communication systems, various types of communication network systems have been developed recently. As one of them, there is the ISDN. The ISDN provides communication services such as telephone service, data communication, facsimile service and so on over the same digital network. For line exchange in a communication system using the ISDN, there is the need for an exchange adapted for the ISDN to which a digital line exchange network, a packet exchange network, a common channel signaling system network and so on are connected. To the ISDN exchange are further connected terminal equipments such as telephone sets, facsimile equipment, voice mail equipment, etc. through a subscriber line network. A plurality of communication channels are time-division multiplexed for each of subscriber lines, and the communication channels are selectively used for communication between terminals. The specifications of the user-network interface of the ISDN are determined as follows.
The interface is classified according to its channel configurations into basic rate interface, primary rate interface, etc. For instance, in the basic rate interface of which transmission rate is 192 Kbps, two 64-Kbps B channels and one 16-Kbps D channel are time-division multiplexed to transmit data or sound. With one of primary rate interfaces (the primary rate B channel interface of which transmission rate is 1544 Kbps), 23 B channels and one D channel of 64 Kbps are multiplexed. Here the B channel refers to an information transferring channel used by user for communication, and the D channel refers to a line switching signaling channel, which is also used as a packet information channel.
In recent years the research and development of communication devices adapted for the ISDN have been conducted energetically, and moreover the activities for adapting a private branch system including a private branch exchange (PBX) to the ISDN are also vigorous so as to implement high-grade sound and data integrated services. A prior example of the private branch exchange accommodated to the ISDN and including digital trunks for ISDN (which are configured as cards) will be described hereinafter.
As shown in FIG. 1, the private branch exchange is basically formed of a line circuit 6 to which a plurality of extension telephones (standard telephone sets, multifunctional telephone sets, etc.) 6a are connected, an analog trunk circuit 7 to which an analog network is connected, and a digital trunk circuit 8 including S interface, T interface, U interface and so on and, to which circuit 8 a digital network such as an ISDN is connected through a network termination 8a. Though not shown, each of line circuit 6 and analog trunk circuit 7 includes a PCM codec operated in response to a PCM clock. Since line circuit 6 and trunk circuits 7 and 8 are each usually disposed on a printed circuit board, they are called the line card and the trunk card. Each of line circuit 6 and trunk circuits 7 and 8 may be provided in plural as needed. A common circuit for controlling line circuit 6 and trunk circuits 7 and 8 for exchange operation includes a time-division switch 3 for performing time-division exchange of internal bus lines in order to exchange PCM data such as sound or data to and from line circuit 6 and trunk circuits 7 and 8 in channel units (one channel comprises 8 bits, and one frame comprises 32 channels) and time-division multiplexes the PCM data and a central control unit 4 comprising a CPU for controlling various operations including the exchange operation. The internal bus lines comprise a CPU control (CTRL) bus, a PCM highway, a frame sync. signal bus, a PCM clock (CLK) bus and a CPU control bus.
Time-division switch 3 requires a clock, i.e., a TSW clock for time-division multiplexing the PCM data. Generally the frequency f of the TSW clock is set at an integral multiple of 64 KHz which corresponds to a channel transmission rate of 64 Kbps. Here f is set at f=12.288 MHz (=64 KHz.times.192). To produce the TSW clock in synchronization with the operation of the digital network, digital trunk circuit 8 extracts 8-KHz clock from a carrier signal of the digital network and applies it to a PLL (phase locked loop) circuit 5, which multiplies the frequency of the extracted clock by 1536 to produce a clock of 12.288 MHz. The 12.288-MHz clock from PLL circuit 5 is usually used as the TSW clock. However, in order for time-division switch 3 to be in operation in case where the output frequency of PLL circuit 5 is deviated because of some failure, an auxiliary oscillator 1 is provided which produces a clock of the same frequency f. One of the outputs from PLL circuit 5 and oscillator 1 is selected by a selector 2 to supply the TSW clock to time-division switch 3. Selector 2 monitors PLL circuit 5 so as to select its output when its output frequency is correct or the output of oscillator 1 when it is not correct.
In FIG. 2 there is shown a block diagram of digital trunk circuit 8. The PCM clock line, PCM highway (transmission, reception) and frame sync. signal line of the internal bus lines are connected to an elastic buffer 9. Elastic buffer 9 is a buffer for suppressing jitters or slips of the PCM clocks, transmit and receive signals over the PCM highway, and the frame sync. signal. Buffer 9 is connected to network termination 8a via digital network interface 10 so as to transmit and receive signals. Interface 10 is connected to a control CPU 11 which is the control center of digital trunk circuit 8. A carrier signal obtained from the digital network through interface 10 is applied to a clock extractor 12 so that a clock of 1.544 MHz is extracted. The clock is, in turn, applied to a mod-193 counter (divide-by-193 circuit) 13 to produce the clock of 8 KHz which is applied to PLL circuit 5.
In such an arrangement, digital trunk circuit 8 communicating with the digital network sends and receives signaling information and PCM information such as sound signals by digital network interface 10 under the control of control CPU 11 in synchronization with a time-division control signal, e.g., the frame sync. signal provided from time-division switch 3. The 8-KHz clock obtained by clock extractor 12 and counter 13 is sent to PLL circuit 5 so that the TSW clock used in a normal operation is produced. That is, so long as digital trunk circuit 8 operates normally, PLL circuit 5 operates in synchronization with the carrier signal sent from the digital network. Hence, the output of PLL circuit 5 is normal and selector 2 selects the output of PLL circuit 5 so that time-division switch 3 operates on the basis of the output of PLL circuit 5. Time-division switch 3 thus responds to the TSW clock to produce predetermined control signals including the frame sync. signal.
The input and output signals of time-division switch 3 are shown in FIG. 3. The TSW clock of 12.288 MHz are divided by 1536 to produce a clock of 8 KHz. The frame sync. signal is obtained based on the 8 KHz clock, which sync. signal has negative pulses with an interval of 125 .mu.s therebetween. The PCM clock start to output in synchronization with the first rising edge of the TSW clock after the falling edge of the frame sync. signal. The PCM clock (2.048 MHz) is obtained by dividing the TSW clock of 12.288 MHz by six. The PCM highway transmits and receives data one bit at a time in synchronization with the PCM clock.
When trunk circuit (card) 8 is unplugged or when a failure occurs in the digital network or trunk circuit 8, the 8-KHz clock is not obtained from trunk circuit 8. PLL circuit 5 will then fail to provide the predetermined output frequency or to provide the output itself. In this case as well, upon detection of abnormality in the output of PLL circuit 5 selector 2 switches connection to time-division switch 3 from PLL circuit 5 to oscillator 1 so as not to stop the supply of the TSW clock to switch 3. It can thus be seen that even when PLL circuit 5 is abnormal, time-division switch 3 is supplied with the output of oscillator 1.
The reason why the output of PLL circuit 5 is used when digital trunk circuit 8 operates properly is to establish phase synchronization between the operation frequency of the exchange and the carrier signal in the digital network. For example, in the primary rate B channel interface the transmission rate of data from the digital network is 1.544 Mbps, and 24 channels, each of 64 Kbps, are multiplexed. That is, in the private branch exchange the PCM data for each of the channels is rewritten at 125-.mu.s intervals in synchronization with the frame sync. signal with a cycle of 125 .mu.s as shown in FIG. 3, and if the private branch exchange is not adapted for a special purpose, the transmission rate per channel over the internal PCM highway is also 64 Kpbs. The transmission and reception of data over the PCM highway must be performed by switching time-division switch 3 with the TSW clock in phase synchronization with the carrier signal in the digital network. However, where time-division switch 3 is operated in response to the clock of frequency f obtained from oscillator 1 of the exchange, a subtle difference between the transmission rate of the PCM data in the exchange and that in the digital network will occurs inevitably, failing to establish the phase synchronization between the exchange and the digital network. In such a case a slip will occur in data transmission in the exchange and the digital network. For example, when the exchange is higher than the digital network in data transmission rate, there is a possibility that the exchange may access same data two times before new data is transmitted from the digital network. On the other hand, when the exchange is lower than the digital network in data transmission rate, there is a possibility that new data ma be sent from the digital network before the exchange accesses old data. The foregoing relates to the case of reception of data. In the case of data transmission as well, the same phenomenon, or the slip occurs.
As described above, the exchange adapted to the ISDN requires a PLL circuit which is operated in synchronization with the clock extracted from the carrier signal transmitted over the digital network in order to avoid occurrence of the slip. The exchange itself disadvantageously becomes expensive and large because of provision of the PLL circuit. For example, in order to support the channel system of a time-division switch having over 300-500 ports with one-stage nonblocking system, the time-division switch requires a high frequency clock of 10 MHz or more as the TSW clock therefor. If the PLL circuit were formed of a digital circuit, a quartz oscillator of the order of 100 MHz would be required. Thus, an analog PLL circuit is generally used which uses a voltage-controlled crystal oscillator. This inevitably makes the exchange bulky and expensive. Moreover, the PLL circuit takes time in frequency tracking. This can adversely affect high speed operation and cause malfunctions due to noise, thus causing low reliability of the exchange.